Static Timing Analysis

Project : Oscilloscope_v1_1
Build Time : 01/17/23 12:17:28
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADCClock(routed) ADCClock(routed) 18.000 MHz 18.000 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 36.000 MHz 36.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 36.000 MHz 36.000 MHz 48.738 MHz
CyTriggerClock CyMASTER_CLK 18.000 MHz 18.000 MHz 44.954 MHz
ADCClock CyMASTER_CLK 18.000 MHz 18.000 MHz N/A
PWM_Clock CyMASTER_CLK 18.000 MHz 18.000 MHz 78.052 MHz
SampleClock CyMASTER_CLK 1.000 MHz 1.000 MHz 89.230 MHz
Noise_Clock CyMASTER_CLK 250.000 kHz 250.000 kHz 70.057 MHz
Wave_Clock CyMASTER_CLK 250.000 kHz 250.000 kHz 127.016 MHz
CyPLL_OUT CyPLL_OUT 36.000 MHz 36.000 MHz N/A
Wave_Clock(routed) Wave_Clock(routed) 250.000 kHz 250.000 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 27.7778ns(36 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 60.816 MHz 16.443 11.335
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.583
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 65.647 MHz 15.233 12.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.583
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cl0 \PWM_Sample_Buffer:PWMUDB:status_0\/main_2 69.716 MHz 14.344 13.434
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cl0 1.520
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.cl0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cl0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb 2.230
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_less\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb \PWM_Sample_Buffer:PWMUDB:status_0\/main_2 7.084
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cl0 \PWM_Sample_Buffer:PWMUDB:prevCompare1\/main_1 69.784 MHz 14.330 13.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cl0 1.520
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.cl0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cl0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb 2.230
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_less\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb \PWM_Sample_Buffer:PWMUDB:prevCompare1\/main_1 7.070
macrocell15 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 71.144 MHz 14.056 13.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/clock_0 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 3.446
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/ce0 \PWM_Sample_Buffer:PWMUDB:status_0\/main_1 71.378 MHz 14.010 13.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/ce0 1.240
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.ce0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/ce0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb 2.270
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_eq\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb \PWM_Sample_Buffer:PWMUDB:status_0\/main_1 6.990
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/ce0 \PWM_Sample_Buffer:PWMUDB:prevCompare1\/main_0 71.495 MHz 13.987 13.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/ce0 1.240
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.ce0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/ce0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb 2.270
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_eq\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb \PWM_Sample_Buffer:PWMUDB:prevCompare1\/main_0 6.967
macrocell15 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_2 75.884 MHz 13.178 14.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:status_2\/main_1 3.588
macrocell4 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:status_2\ \PWM_Sample_Buffer:PWMUDB:status_2\/main_1 \PWM_Sample_Buffer:PWMUDB:status_2\/q 3.350
Route 1 \PWM_Sample_Buffer:PWMUDB:status_2\ \PWM_Sample_Buffer:PWMUDB:status_2\/q \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_2 2.240
statusicell1 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 76.086 MHz 13.143 14.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.583
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb \PWM_Sample_Buffer:PWMUDB:status_0\/main_2 76.313 MHz 13.104 14.674
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb 2.510
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_less\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cl0_comb \PWM_Sample_Buffer:PWMUDB:status_0\/main_2 7.084
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_600/q \Trigger_Status:sts:sts_reg\/status_2 87.040 MHz 11.489 16.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_509/main_0 4.086
macrocell8 U(3,2) 1 Net_509 Net_509/main_0 Net_509/q 3.350
Route 1 Net_509 Net_509/q \Trigger_Status:sts:sts_reg\/status_2 2.303
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Trigger_Block/q \Trigger_Status:sts:sts_reg\/status_1 93.958 MHz 10.643 17.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,3) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q Net_510/main_2 3.227
macrocell7 U(2,2) 1 Net_510 Net_510/main_2 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 125.203 MHz 7.987 19.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,3) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 3.227
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
Net_600/q Net_601/main_1 125.992 MHz 7.937 19.841
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_601/main_1 3.177
macrocell19 U(2,1) 1 Net_601 SETUP 3.510
Clock Skew 0.000
Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 126.088 MHz 7.931 19.847
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 3.171
macrocell21 U(3,1) 1 \EdgeDetect_CaptureComplete:last\ SETUP 3.510
Clock Skew 0.000
Net_600/q Net_550/main_2 126.422 MHz 7.910 19.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_550/main_2 3.150
macrocell22 U(2,1) 1 Net_550 SETUP 3.510
Clock Skew 0.000
External_Trigger(0)_SYNC/out Net_550/main_3 134.084 MHz 7.458 20.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 External_Trigger(0)_SYNC External_Trigger(0)_SYNC/clock External_Trigger(0)_SYNC/out 1.020
Route 1 Net_533_SYNCOUT External_Trigger(0)_SYNC/out Net_550/main_3 2.928
macrocell22 U(2,1) 1 Net_550 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 127.016 MHz 7.873 19.905
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,4) 1 \Wave_Control:Sync:ctrl_reg\ \Wave_Control:Sync:ctrl_reg\/busclk \Wave_Control:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_564 \Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 2.313
macrocell30 U(2,4) 1 \Wave_DAC:Net_134\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_3 Net_641/main_0 48.738 MHz 20.518 7.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.818
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 3.995
macrocell31 U(2,3) 1 Net_641 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 Net_205/main_0 48.738 MHz 20.518 7.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.818
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 3.995
macrocell33 U(2,3) 1 Net_205 SETUP 3.510
Clock Skew 0.000
Net_550/q Net_641/main_0 48.745 MHz 20.515 7.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,1) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.775
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 3.995
macrocell31 U(2,3) 1 Net_641 SETUP 3.510
Clock Skew 0.000
Net_550/q Net_205/main_0 48.745 MHz 20.515 7.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,1) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.775
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 3.995
macrocell33 U(2,3) 1 Net_205 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 Net_641/main_0 48.752 MHz 20.512 7.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 1.210
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger_split/main_0 2.812
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_0 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 3.995
macrocell31 U(2,3) 1 Net_641 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 Net_205/main_0 48.752 MHz 20.512 7.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 1.210
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger_split/main_0 2.812
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_0 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 3.995
macrocell33 U(2,3) 1 Net_205 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 Net_641/main_0 49.171 MHz 20.337 7.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.637
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 3.995
macrocell31 U(2,3) 1 Net_641 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 Net_205/main_0 49.171 MHz 20.337 7.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.637
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 3.995
macrocell33 U(2,3) 1 Net_205 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 Net_641/main_0 49.176 MHz 20.335 7.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 2.635
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 3.995
macrocell31 U(2,3) 1 Net_641 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 Net_205/main_0 49.176 MHz 20.335 7.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 2.635
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 3.995
macrocell33 U(2,3) 1 Net_205 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 55.5556ns(18 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_3 \Trigger_Status:sts:sts_reg\/status_1 44.954 MHz 22.245 33.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.818
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 3.066
macrocell7 U(2,2) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Net_550/q \Trigger_Status:sts:sts_reg\/status_1 44.960 MHz 22.242 33.314
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,1) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.775
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 3.066
macrocell7 U(2,2) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 \Trigger_Status:sts:sts_reg\/status_1 44.966 MHz 22.239 33.317
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 1.210
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger_split/main_0 2.812
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_0 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 3.066
macrocell7 U(2,2) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \Trigger_Status:sts:sts_reg\/status_1 45.323 MHz 22.064 33.492
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.637
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 3.066
macrocell7 U(2,2) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \Trigger_Status:sts:sts_reg\/status_1 45.327 MHz 22.062 33.494
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 2.635
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 3.066
macrocell7 U(2,2) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 \EdgeDetect_Trigger:last\/main_0 51.049 MHz 19.589 35.967
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.818
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
Net_550/q \EdgeDetect_Trigger:last\/main_0 51.057 MHz 19.586 35.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,1) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.775
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 \EdgeDetect_Trigger:last\/main_0 51.065 MHz 19.583 35.973
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 1.210
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger_split/main_0 2.812
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_0 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \EdgeDetect_Trigger:last\/main_0 51.525 MHz 19.408 36.148
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.637
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \EdgeDetect_Trigger:last\/main_0 51.530 MHz 19.406 36.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 2.635
macrocell1 U(3,1) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.285
macrocell3 U(3,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 4000ns(250 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/sir 70.057 MHz 14.274 3985.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.084
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/sol_msb 6.960
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 3.020
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cfbi 73.346 MHz 13.634 3986.366
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.084
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/cfbo 3.450
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 5.890
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 78.635 MHz 12.717 3987.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 3.377
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 8.130
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 80.489 MHz 12.424 3987.576
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.084
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ SETUP 8.130
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/sir 98.814 MHz 10.120 3989.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 1.540
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/sol_msb 5.560
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 3.020
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/cfbi 99.010 MHz 10.100 3989.900
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 1.540
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/cfbo 2.670
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 5.890
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 120.919 MHz 8.270 3991.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 1.540
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ SETUP 6.730
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 149.656 MHz 6.682 3993.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 3.372
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 2.100
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 149.678 MHz 6.681 3993.319
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 3.371
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ SETUP 2.100
Clock Skew 0.000
\PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 155.521 MHz 6.430 3993.570
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/clock \PRS:sC16:PRSdp:u0\/sol_msb 3.410
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ SETUP 3.020
Clock Skew 0.000
Path Delay Requirement : 55.5556ns(18 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 78.052 MHz 12.812 42.744
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.462
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 83.584 MHz 11.964 43.592
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \Digital_PWM:PWMUDB:tc_i\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:status_2\/main_1 3.504
macrocell11 U(0,1) 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/main_1 \Digital_PWM:PWMUDB:status_2\/q 3.350
Route 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 2.320
statusicell2 U(0,1) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 99.830 MHz 10.017 45.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(0,1) 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/clock_0 \Digital_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:status_2\/main_0 2.597
macrocell11 U(0,1) 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/main_0 \Digital_PWM:PWMUDB:status_2\/q 3.350
Route 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 2.320
statusicell2 U(0,1) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 100.847 MHz 9.916 45.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(0,1) 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/clock_0 \Digital_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.606
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_885/main_1 115.996 MHz 8.621 46.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_885/main_1 2.601
macrocell41 U(0,1) 1 Net_885 SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 116.117 MHz 8.612 46.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 2.592
macrocell37 U(0,1) 1 \Digital_PWM:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 116.117 MHz 8.612 46.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 2.592
macrocell39 U(0,1) 1 \Digital_PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 117.014 MHz 8.546 47.010
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 2.430
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 2.606
macrocell42 U(0,1) 1 Net_916 SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 117.123 MHz 8.538 47.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 2.430
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 2.598
macrocell38 U(0,1) 1 \Digital_PWM:PWMUDB:prevCompare2\ SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 117.123 MHz 8.538 47.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 2.430
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 2.598
macrocell40 U(0,1) 1 \Digital_PWM:PWMUDB:status_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_4\/main_0 89.230 MHz 11.207 988.793
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,2) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_4\/main_0 6.447
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_0\/q Net_1476/main_7 89.469 MHz 11.177 988.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,3) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q Net_1476/main_7 6.417
macrocell12 U(3,2) 1 Net_1476 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_3\/q Net_1476/main_4 93.266 MHz 10.722 989.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q Net_1476/main_4 5.962
macrocell12 U(3,2) 1 Net_1476 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_3\/main_0 93.958 MHz 10.643 989.357
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,2) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_3\/main_0 5.883
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_2\/main_3 98.580 MHz 10.144 989.856
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_2\/main_3 5.384
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_4\/main_4 98.600 MHz 10.142 989.858
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,3) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_4\/main_4 5.382
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_5\/main_0 102.124 MHz 9.792 990.208
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,2) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_5\/main_0 5.032
macrocell24 U(3,3) 1 \FreqDiv_1:count_5\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_2\/main_6 102.135 MHz 9.791 990.209
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,3) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_2\/main_6 5.031
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_1\/q \FreqDiv_1:count_4\/main_3 103.466 MHz 9.665 990.335
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,3) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q \FreqDiv_1:count_4\/main_3 4.905
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_1\/q \FreqDiv_1:count_2\/main_5 103.595 MHz 9.653 990.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,3) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q \FreqDiv_1:count_2\/main_5 4.893
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 2.140
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_1 2.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\ \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/clock \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_Sample_Buffer:PWMUDB:control_7\ \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_1 2.269
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\Sync_5:genblk1[0]:INST\/out Net_641/main_4 3.445
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \Sync_5:genblk1[0]:INST\ \Sync_5:genblk1[0]:INST\/clock \Sync_5:genblk1[0]:INST\/out 0.350
Route 1 Net_656 \Sync_5:genblk1[0]:INST\/out Net_641/main_4 3.095
macrocell31 U(2,3) 1 Net_641 HOLD 0.000
Clock Skew 0.000
\Sync_5:genblk1[0]:INST\/out Net_205/main_4 3.445
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \Sync_5:genblk1[0]:INST\ \Sync_5:genblk1[0]:INST\/clock \Sync_5:genblk1[0]:INST\/out 0.350
Route 1 Net_656 \Sync_5:genblk1[0]:INST\/out Net_205/main_4 3.095
macrocell33 U(2,3) 1 Net_205 HOLD 0.000
Clock Skew 0.000
\Sync_5:genblk1[0]:INST\/out \EdgeDetect_1:last\/main_0 3.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \Sync_5:genblk1[0]:INST\ \Sync_5:genblk1[0]:INST\/clock \Sync_5:genblk1[0]:INST\/out 0.350
Route 1 Net_656 \Sync_5:genblk1[0]:INST\/out \EdgeDetect_1:last\/main_0 3.106
macrocell34 U(2,3) 1 \EdgeDetect_1:last\ HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:trig_last\/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_2 3.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ \PWM_Sample_Buffer:PWMUDB:trig_last\/clock_0 \PWM_Sample_Buffer:PWMUDB:trig_last\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ \PWM_Sample_Buffer:PWMUDB:trig_last\/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_2 2.228
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:prevCompare1\/q \PWM_Sample_Buffer:PWMUDB:status_0\/main_0 3.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ \PWM_Sample_Buffer:PWMUDB:prevCompare1\/clock_0 \PWM_Sample_Buffer:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ \PWM_Sample_Buffer:PWMUDB:prevCompare1\/q \PWM_Sample_Buffer:PWMUDB:status_0\/main_0 2.284
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
Net_641/q Net_641/main_1 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,3) 1 Net_641 Net_641/clock_0 Net_641/q 1.250
macrocell31 U(2,3) 1 Net_641 Net_641/q Net_641/main_1 2.290
macrocell31 U(2,3) 1 Net_641 HOLD 0.000
Clock Skew 0.000
Net_641/q Net_205/main_1 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,3) 1 Net_641 Net_641/clock_0 Net_641/q 1.250
Route 1 Net_641 Net_641/q Net_205/main_1 2.290
macrocell33 U(2,3) 1 Net_205 HOLD 0.000
Clock Skew 0.000
Net_633/q Net_633/main_3 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,2) 1 Net_633 Net_633/clock_0 Net_633/q 1.250
macrocell32 U(2,2) 1 Net_633 Net_633/q Net_633/main_3 2.292
macrocell32 U(2,2) 1 Net_633 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
External_Trigger(0)_SYNC/out Net_550/main_3 3.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,2) 1 External_Trigger(0)_SYNC External_Trigger(0)_SYNC/clock External_Trigger(0)_SYNC/out 0.350
Route 1 Net_533_SYNCOUT External_Trigger(0)_SYNC/out Net_550/main_3 2.928
macrocell22 U(2,1) 1 Net_550 HOLD 0.000
Clock Skew 0.000
Net_600/q Net_550/main_2 4.400
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_550/main_2 3.150
macrocell22 U(2,1) 1 Net_550 HOLD 0.000
Clock Skew 0.000
Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 4.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 3.171
macrocell21 U(3,1) 1 \EdgeDetect_CaptureComplete:last\ HOLD 0.000
Clock Skew 0.000
Net_600/q Net_601/main_1 4.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_601/main_1 3.177
macrocell19 U(2,1) 1 Net_601 HOLD 0.000
Clock Skew 0.000
Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 4.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,3) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 3.227
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
Trigger_Block/q \Trigger_Status:sts:sts_reg\/status_1 8.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,3) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q Net_510/main_2 3.227
macrocell7 U(2,2) 1 Net_510 Net_510/main_2 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
Net_600/q \Trigger_Status:sts:sts_reg\/status_2 8.989
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,0) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_509/main_0 4.086
macrocell8 U(3,2) 1 Net_509 Net_509/main_0 Net_509/q 3.350
Route 1 Net_509 Net_509/q \Trigger_Status:sts:sts_reg\/status_2 2.303
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 2.933
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,4) 1 \Wave_Control:Sync:ctrl_reg\ \Wave_Control:Sync:ctrl_reg\/busclk \Wave_Control:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_564 \Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 2.313
macrocell30 U(2,4) 1 \Wave_DAC:Net_134\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_6 Net_633/main_0 3.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_6 0.360
Route 1 ARM \Trigger_Control:Sync:ctrl_reg\/control_6 Net_633/main_0 3.376
macrocell32 U(2,2) 1 Net_633 HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 5.518
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 5.158
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_0 6.050
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_0 5.690
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 6.529
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 6.169
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 6.719
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 6.359
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.360
statusicell1 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 7.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 5.158
datapathcell1 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 1.790
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 9.211
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 0.360
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger/main_2 2.621
macrocell3 U(3,1) 1 Trigger Trigger/main_2 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 2.880
macrocell13 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 9.211
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 0.360
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger/main_2 2.621
macrocell3 U(3,1) 1 Trigger Trigger/main_2 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 2.880
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 9.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 0.360
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger/main_1 2.623
macrocell3 U(3,1) 1 Trigger Trigger/main_1 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 2.880
macrocell13 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_4 Net_550/main_0 2.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_4 0.360
Route 1 Net_265 \Trigger_Control:Sync:ctrl_reg\/control_4 Net_550/main_0 2.319
macrocell22 U(2,1) 1 Net_550 HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_6 Net_601/main_0 2.984
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_6 0.360
Route 1 ARM \Trigger_Control:Sync:ctrl_reg\/control_6 Net_601/main_0 2.624
macrocell19 U(2,1) 1 Net_601 HOLD 0.000
Clock Skew 0.000
Net_601/q Net_601/main_2 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,1) 1 Net_601 Net_601/clock_0 Net_601/q 1.250
macrocell19 U(2,1) 1 Net_601 Net_601/q Net_601/main_2 2.297
macrocell19 U(2,1) 1 Net_601 HOLD 0.000
Clock Skew 0.000
Net_550/q Net_550/main_1 4.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,1) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
macrocell22 U(2,1) 1 Net_550 Net_550/q Net_550/main_1 2.771
macrocell22 U(2,1) 1 Net_550 HOLD 0.000
Clock Skew 0.000
\EdgeDetect_Trigger:last\/q \Trigger_Status:sts:sts_reg\/status_1 7.204
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ \EdgeDetect_Trigger:last\/clock_0 \EdgeDetect_Trigger:last\/q 1.250
Route 1 \EdgeDetect_Trigger:last\ \EdgeDetect_Trigger:last\/q Net_510/main_1 2.288
macrocell7 U(2,2) 1 Net_510 Net_510/main_1 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
\EdgeDetect_CaptureComplete:last\/q \Trigger_Status:sts:sts_reg\/status_2 7.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,1) 1 \EdgeDetect_CaptureComplete:last\ \EdgeDetect_CaptureComplete:last\/clock_0 \EdgeDetect_CaptureComplete:last\/q 1.250
Route 1 \EdgeDetect_CaptureComplete:last\ \EdgeDetect_CaptureComplete:last\/q Net_509/main_1 2.907
macrocell8 U(3,2) 1 Net_509 Net_509/main_1 Net_509/q 3.350
Route 1 Net_509 Net_509/q \Trigger_Status:sts:sts_reg\/status_2 2.303
statuscell1 U(3,2) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \EdgeDetect_Trigger:last\/main_0 9.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 0.360
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger/main_2 2.621
macrocell3 U(3,1) 1 Trigger Trigger/main_2 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \EdgeDetect_Trigger:last\/main_0 9.399
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 0.360
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger/main_1 2.623
macrocell3 U(3,1) 1 Trigger Trigger/main_1 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 \EdgeDetect_Trigger:last\/main_0 9.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 0.360
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger/main_0 2.811
macrocell3 U(3,1) 1 Trigger Trigger/main_0 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 \EdgeDetect_Trigger:last\/main_0 9.597
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 0.360
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger/main_3 2.821
macrocell3 U(3,1) 1 Trigger Trigger/main_3 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 3.066
macrocell20 U(2,2) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.580
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 0.580
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 1.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/clock \PRS:sC16:PRSdp:u0\/sol_msb 1.070
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/cfbi 1.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 0.580
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/cfbo 1.270
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/sir 2.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 0.580
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/sol_msb 2.250
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.084
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 3.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 3.371
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 3.732
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 3.372
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 3.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 3.377
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cfbi 4.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.084
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/cfbo 1.080
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/sir 5.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.084
datapathcell3 U(2,3) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/sol_msb 1.750
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,3) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Digital_PWM:PWMUDB:status_1\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_1 1.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,1) 1 \Digital_PWM:PWMUDB:status_1\ \Digital_PWM:PWMUDB:status_1\/clock_0 \Digital_PWM:PWMUDB:status_1\/q 1.250
Route 1 \Digital_PWM:PWMUDB:status_1\ \Digital_PWM:PWMUDB:status_1\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_1 2.321
statusicell2 U(0,1) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:status_0\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,1) 1 \Digital_PWM:PWMUDB:status_0\ \Digital_PWM:PWMUDB:status_0\/clock_0 \Digital_PWM:PWMUDB:status_0\/q 1.250
Route 1 \Digital_PWM:PWMUDB:status_0\ \Digital_PWM:PWMUDB:status_0\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_0 2.323
statusicell2 U(0,1) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:genblk1:ctrlreg\/control_7 \Digital_PWM:PWMUDB:runmode_enable\/main_0 2.709
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Digital_PWM:PWMUDB:genblk1:ctrlreg\ \Digital_PWM:PWMUDB:genblk1:ctrlreg\/clock \Digital_PWM:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \Digital_PWM:PWMUDB:control_7\ \Digital_PWM:PWMUDB:genblk1:ctrlreg\/control_7 \Digital_PWM:PWMUDB:runmode_enable\/main_0 2.349
macrocell36 U(0,1) 1 \Digital_PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 3.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 2.592
macrocell37 U(0,1) 1 \Digital_PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 3.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 2.592
macrocell39 U(0,1) 1 \Digital_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_885/main_1 3.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_885/main_1 2.601
macrocell41 U(0,1) 1 Net_885 HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 3.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 0.810
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 2.598
macrocell38 U(0,1) 1 \Digital_PWM:PWMUDB:prevCompare2\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 3.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 0.810
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 2.598
macrocell40 U(0,1) 1 \Digital_PWM:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 3.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,1) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 0.810
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 2.606
macrocell42 U(0,1) 1 Net_916 HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:prevCompare1\/q \Digital_PWM:PWMUDB:status_0\/main_0 3.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(0,1) 1 \Digital_PWM:PWMUDB:prevCompare1\ \Digital_PWM:PWMUDB:prevCompare1\/clock_0 \Digital_PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \Digital_PWM:PWMUDB:prevCompare1\ \Digital_PWM:PWMUDB:prevCompare1\/q \Digital_PWM:PWMUDB:status_0\/main_0 2.291
macrocell39 U(0,1) 1 \Digital_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\FreqDiv_1:count_5\/q \FreqDiv_1:count_5\/main_1 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,3) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
macrocell24 U(3,3) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q \FreqDiv_1:count_5\/main_1 2.293
macrocell24 U(3,3) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
Net_1476/q Net_1476/main_0 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 Net_1476 Net_1476/clock_0 Net_1476/q 1.250
macrocell12 U(3,2) 1 Net_1476 Net_1476/q Net_1476/main_0 2.295
macrocell12 U(3,2) 1 Net_1476 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_4\/q \FreqDiv_1:count_3\/main_2 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
Route 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q \FreqDiv_1:count_3\/main_2 2.308
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_4\/main_1 3.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_4\/main_1 2.582
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_3\/main_3 3.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_3\/main_3 2.585
macrocell26 U(3,4) 1 \FreqDiv_1:count_3\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_1\/q \FreqDiv_1:count_5\/main_5 3.883
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,3) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q \FreqDiv_1:count_5\/main_5 2.633
macrocell24 U(3,3) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q Net_1476/main_5 4.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
Route 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q Net_1476/main_5 2.771
macrocell12 U(3,2) 1 Net_1476 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q \FreqDiv_1:count_2\/main_4 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q \FreqDiv_1:count_2\/main_4 2.775
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_2\/main_0 4.164
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,2) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_2\/main_0 2.914
macrocell27 U(3,2) 1 \FreqDiv_1:count_2\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q Net_1476/main_1 4.169
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,2) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q Net_1476/main_1 2.919
macrocell12 U(3,2) 1 Net_1476 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Digital_Out_Control:Sync:ctrl_reg\/control_2 DigOut_3(0)_PAD 25.358
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_229 \Digital_Out_Control:Sync:ctrl_reg\/control_2 DigOut_3(0)/pin_input 7.383
iocell17 P15[5] 1 DigOut_3(0) DigOut_3(0)/pin_input DigOut_3(0)/pad_out 15.925
Route 1 DigOut_3(0)_PAD DigOut_3(0)/pad_out DigOut_3(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_4 DigOut_5(0)_PAD 24.273
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_232 \Digital_Out_Control:Sync:ctrl_reg\/control_4 DigOut_5(0)/pin_input 6.421
iocell21 P0[1] 1 DigOut_5(0) DigOut_5(0)/pin_input DigOut_5(0)/pad_out 15.802
Route 1 DigOut_5(0)_PAD DigOut_5(0)/pad_out DigOut_5(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_6 DigOut_7(0)_PAD 23.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_234 \Digital_Out_Control:Sync:ctrl_reg\/control_6 DigOut_7(0)/pin_input 6.261
iocell23 P0[6] 1 DigOut_7(0) DigOut_7(0)/pin_input DigOut_7(0)/pad_out 15.561
Route 1 DigOut_7(0)_PAD DigOut_7(0)/pad_out DigOut_7(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_7 DigOut_8(0)_PAD 23.819
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_7 2.050
Route 1 Net_237 \Digital_Out_Control:Sync:ctrl_reg\/control_7 DigOut_8(0)/pin_input 6.274
iocell24 P0[7] 1 DigOut_8(0) DigOut_8(0)/pin_input DigOut_8(0)/pad_out 15.495
Route 1 DigOut_8(0)_PAD DigOut_8(0)/pad_out DigOut_8(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_1 DigOut_2(0)_PAD 23.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_228 \Digital_Out_Control:Sync:ctrl_reg\/control_1 DigOut_2(0)/pin_input 7.336
iocell11 P15[1] 1 DigOut_2(0) DigOut_2(0)/pin_input DigOut_2(0)/pad_out 14.429
Route 1 DigOut_2(0)_PAD DigOut_2(0)/pad_out DigOut_2(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_0 DigOut_1(0)_PAD 23.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_231 \Digital_Out_Control:Sync:ctrl_reg\/control_0 DigOut_1(0)/pin_input 7.346
iocell10 P15[0] 1 DigOut_1(0) DigOut_1(0)/pin_input DigOut_1(0)/pad_out 14.255
Route 1 DigOut_1(0)_PAD DigOut_1(0)/pad_out DigOut_1(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_5 DigOut_6(0)_PAD 23.467
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_233 \Digital_Out_Control:Sync:ctrl_reg\/control_5 DigOut_6(0)/pin_input 6.394
iocell9 P0[5] 1 DigOut_6(0) DigOut_6(0)/pin_input DigOut_6(0)/pad_out 15.023
Route 1 DigOut_6(0)_PAD DigOut_6(0)/pad_out DigOut_6(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_3 DigOut_4(0)_PAD 22.781
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,4) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_230 \Digital_Out_Control:Sync:ctrl_reg\/control_3 DigOut_4(0)/pin_input 5.480
iocell18 P0[0] 1 DigOut_4(0) DigOut_4(0)/pin_input DigOut_4(0)/pad_out 15.251
Route 1 DigOut_4(0)_PAD DigOut_4(0)/pad_out DigOut_4(0)_PAD 0.000
Clock Clock path delay 0.000
+ PWM_Clock
Source Destination Delay (ns)
Net_916/q PWMOutB_0(0)_PAD 23.294
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(0,1) 1 Net_916 Net_916/clock_0 Net_916/q 1.250
Route 1 Net_916 Net_916/q PWMOutB_0(0)/pin_input 6.366
iocell16 P1[4] 1 PWMOutB_0(0) PWMOutB_0(0)/pin_input PWMOutB_0(0)/pad_out 15.678
Route 1 PWMOutB_0(0)_PAD PWMOutB_0(0)/pad_out PWMOutB_0(0)_PAD 0.000
Clock Clock path delay 0.000
Net_885/q PWMOut_0(0)_PAD 23.118
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(0,1) 1 Net_885 Net_885/clock_0 Net_885/q 1.250
Route 1 Net_885 Net_885/q PWMOut_0(0)/pin_input 6.398
iocell15 P1[2] 1 PWMOut_0(0) PWMOut_0(0)/pin_input PWMOut_0(0)/pad_out 15.470
Route 1 PWMOut_0(0)_PAD PWMOut_0(0)/pad_out PWMOut_0(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 132.100 MHz 7.570 20.208
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 1.210
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.360
statusicell1 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 132.118 MHz 7.569 20.209
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 1.210
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 6.359
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ RECOVERY -0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 135.520 MHz 7.379 20.399
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 1.210
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 6.169
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 6.529
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 6.169
macrocell16 U(1,1) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 6.719
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 6.359
macrocell14 U(2,0) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,1) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.360
statusicell1 U(3,0) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ REMOVAL 0.000
Clock Skew 0.000