Static Timing Analysis

Project : OScope
Build Time : 08/17/22 10:44:31
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADCClock(routed) ADCClock(routed) 18.000 MHz 18.000 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 36.000 MHz 36.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 36.000 MHz 36.000 MHz 45.455 MHz
CyTriggerClock CyMASTER_CLK 18.000 MHz 18.000 MHz 38.914 MHz
ADCClock CyMASTER_CLK 18.000 MHz 18.000 MHz N/A
PWM_Clock CyMASTER_CLK 18.000 MHz 18.000 MHz 90.326 MHz
SampleClock CyMASTER_CLK 1.000 MHz 1.000 MHz 104.646 MHz
Noise_Clock CyMASTER_CLK 250.000 kHz 250.000 kHz 67.801 MHz
Wave_Clock CyMASTER_CLK 250.000 kHz 250.000 kHz 126.839 MHz
CyPLL_OUT CyPLL_OUT 36.000 MHz 36.000 MHz N/A
Wave_Clock(routed) Wave_Clock(routed) 250.000 kHz 250.000 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 27.7778ns(36 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 60.994 MHz 16.395 11.383
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.535
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 64.251 MHz 15.564 12.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/clock_0 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 4.954
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 65.854 MHz 15.185 12.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.535
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 5.130
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 4.230
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_2 75.523 MHz 13.241 14.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:status_2\/main_1 3.588
macrocell4 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:status_2\ \PWM_Sample_Buffer:PWMUDB:status_2\/main_1 \PWM_Sample_Buffer:PWMUDB:status_2\/q 3.350
Route 1 \PWM_Sample_Buffer:PWMUDB:status_2\ \PWM_Sample_Buffer:PWMUDB:status_2\/q \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_2 2.303
statusicell1 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 76.365 MHz 13.095 14.683
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.535
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 81.539 MHz 12.264 15.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/clock_0 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_1 4.954
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 82.068 MHz 12.185 15.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 0.760
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.z0__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/z0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0i \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.740
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_2 2.625
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 6.060
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_2 83.119 MHz 12.031 15.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:status_2\/main_1 3.588
macrocell4 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:status_2\ \PWM_Sample_Buffer:PWMUDB:status_2\/main_1 \PWM_Sample_Buffer:PWMUDB:status_2\/q 3.350
Route 1 \PWM_Sample_Buffer:PWMUDB:status_2\ \PWM_Sample_Buffer:PWMUDB:status_2\/q \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_2 2.303
statusicell1 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 84.140 MHz 11.885 15.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb 2.290
Route 1 \PWM_Sample_Buffer:PWMUDB:tc_i\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/z0_comb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_2 3.535
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_1 88.145 MHz 11.345 16.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/clock_0 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ \PWM_Sample_Buffer:PWMUDB:runmode_enable\/q \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_1 4.035
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ SETUP 6.060
Clock Skew 0.000
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_600/q \Trigger_Status:sts:sts_reg\/status_2 86.633 MHz 11.543 16.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_509/main_0 4.140
macrocell8 U(3,3) 1 Net_509 Net_509/main_0 Net_509/q 3.350
Route 1 Net_509 Net_509/q \Trigger_Status:sts:sts_reg\/status_2 2.303
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Trigger_Block/q \Trigger_Status:sts:sts_reg\/status_1 86.806 MHz 11.520 16.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,1) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q Net_510/main_2 4.104
macrocell7 U(2,3) 1 Net_510 Net_510/main_2 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 112.816 MHz 8.864 18.914
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,1) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 4.104
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 125.219 MHz 7.986 19.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 3.226
macrocell21 U(3,2) 1 \EdgeDetect_CaptureComplete:last\ SETUP 3.510
Clock Skew 0.000
Net_600/q Net_550/main_2 125.219 MHz 7.986 19.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_550/main_2 3.226
macrocell22 U(3,2) 1 Net_550 SETUP 3.510
Clock Skew 0.000
Net_600/q Net_601/main_1 125.534 MHz 7.966 19.812
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_601/main_1 3.206
macrocell19 U(3,0) 1 Net_601 SETUP 3.510
Clock Skew 0.000
External_Trigger(0)_SYNC/out Net_550/main_3 134.680 MHz 7.425 20.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 External_Trigger(0)_SYNC External_Trigger(0)_SYNC/clock External_Trigger(0)_SYNC/out 1.020
Route 1 Net_533_SYNCOUT External_Trigger(0)_SYNC/out Net_550/main_3 2.895
macrocell22 U(3,2) 1 Net_550 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 126.839 MHz 7.884 19.894
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,3) 1 \Wave_Control:Sync:ctrl_reg\ \Wave_Control:Sync:ctrl_reg\/busclk \Wave_Control:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_564 \Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 2.324
macrocell30 U(2,3) 1 \Wave_DAC:Net_134\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_2 \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 45.455 MHz 22.000 5.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 3.519
macrocell13 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 45.455 MHz 22.000 5.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 3.519
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 Net_641/main_0 46.733 MHz 21.398 6.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 2.917
macrocell31 U(2,1) 1 Net_641 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 Net_633/main_1 46.736 MHz 21.397 6.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_633/main_1 2.916
macrocell32 U(2,1) 1 Net_633 SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 Net_205/main_0 46.736 MHz 21.397 6.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 2.916
macrocell33 U(2,1) 1 Net_205 SETUP 3.510
Clock Skew 0.000
Net_550/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 48.333 MHz 20.690 7.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,2) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.786
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 3.519
macrocell13 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ SETUP 3.510
Clock Skew 0.000
Net_550/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 48.333 MHz 20.690 7.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,2) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.786
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 3.519
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 48.792 MHz 20.495 7.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.631
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 3.519
macrocell13 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 48.792 MHz 20.495 7.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.631
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_0 3.519
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 48.797 MHz 20.493 7.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.629
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \PWM_Sample_Buffer:PWMUDB:trig_last\/main_0 3.519
macrocell13 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 55.5556ns(18 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_2 \Trigger_Status:sts:sts_reg\/status_1 38.914 MHz 25.698 29.858
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 4.561
macrocell7 U(2,3) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Net_550/q \Trigger_Status:sts:sts_reg\/status_1 41.004 MHz 24.388 31.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,2) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.786
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 4.561
macrocell7 U(2,3) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \Trigger_Status:sts:sts_reg\/status_1 41.334 MHz 24.193 31.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.631
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 4.561
macrocell7 U(2,3) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 \Trigger_Status:sts:sts_reg\/status_1 41.338 MHz 24.191 31.365
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.629
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 4.561
macrocell7 U(2,3) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 \Trigger_Status:sts:sts_reg\/status_1 41.887 MHz 23.874 31.682
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 1.210
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger_split/main_0 2.312
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_0 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 4.561
macrocell7 U(2,3) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \EdgeDetect_Trigger:last\/main_0 43.399 MHz 23.042 32.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger_split/main_2 4.136
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_2 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
Net_550/q \EdgeDetect_Trigger:last\/main_0 46.015 MHz 21.732 33.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,2) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
Route 1 Net_550 Net_550/q Trigger_split/main_6 2.786
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_6 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \EdgeDetect_Trigger:last\/main_0 46.432 MHz 21.537 34.019
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 1.210
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger_split/main_1 2.631
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_1 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 \EdgeDetect_Trigger:last\/main_0 46.436 MHz 21.535 34.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 1.210
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger_split/main_3 2.629
macrocell1 U(2,2) 1 Trigger_split Trigger_split/main_3 Trigger_split/q 3.350
Route 1 Trigger_split Trigger_split/q Trigger/main_6 2.925
macrocell3 U(2,1) 1 Trigger Trigger/main_6 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ SETUP 3.510
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \Trigger_Status:sts:sts_reg\/status_1 46.468 MHz 21.520 34.036
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 1.210
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger/main_2 6.233
macrocell3 U(2,1) 1 Trigger Trigger/main_2 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_510/main_0 4.561
macrocell7 U(2,3) 1 Net_510 Net_510/main_0 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 4000ns(250 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/sir 67.801 MHz 14.749 3985.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.559
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/sol_msb 6.960
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 3.020
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cfbi 70.877 MHz 14.109 3985.891
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.559
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/cfbo 3.450
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 5.890
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 77.220 MHz 12.950 3987.050
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 3.610
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 8.130
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 77.525 MHz 12.899 3987.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.559
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ SETUP 8.130
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/sir 98.814 MHz 10.120 3989.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 1.540
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/sol_msb 5.560
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 3.020
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/cfbi 99.010 MHz 10.100 3989.900
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 1.540
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/cfbo 2.670
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 5.890
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 120.919 MHz 8.270 3991.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 1.540
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ SETUP 6.730
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 144.676 MHz 6.912 3993.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 3.602
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 2.100
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 145.012 MHz 6.896 3993.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 1.210
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 3.586
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ SETUP 2.100
Clock Skew 0.000
\PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 155.521 MHz 6.430 3993.570
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/clock \PRS:sC16:PRSdp:u0\/sol_msb 3.410
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ SETUP 3.020
Clock Skew 0.000
Path Delay Requirement : 55.5556ns(18 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 90.326 MHz 11.071 44.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \Digital_PWM:PWMUDB:tc_i\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:status_2\/main_1 2.676
macrocell11 U(0,0) 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/main_1 \Digital_PWM:PWMUDB:status_2\/q 3.350
Route 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 2.255
statusicell2 U(0,0) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 90.645 MHz 11.032 44.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.682
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 94.464 MHz 10.586 44.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(0,0) 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/clock_0 \Digital_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.276
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 96.562 MHz 10.356 45.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(0,0) 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/clock_0 \Digital_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \Digital_PWM:PWMUDB:runmode_enable\ \Digital_PWM:PWMUDB:runmode_enable\/q \Digital_PWM:PWMUDB:status_2\/main_0 3.001
macrocell11 U(0,0) 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/main_0 \Digital_PWM:PWMUDB:status_2\/q 3.350
Route 1 \Digital_PWM:PWMUDB:status_2\ \Digital_PWM:PWMUDB:status_2\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_2 2.255
statusicell2 U(0,0) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_885/main_1 112.829 MHz 8.863 46.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_885/main_1 2.843
macrocell41 U(1,0) 1 Net_885 SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 112.880 MHz 8.859 46.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 2.839
macrocell37 U(0,0) 1 \Digital_PWM:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 113.045 MHz 8.846 46.710
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 2.826
macrocell39 U(0,0) 1 \Digital_PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 117.980 MHz 8.476 47.080
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 2.430
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 2.536
macrocell42 U(0,0) 1 Net_916 SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 118.092 MHz 8.468 47.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 2.430
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 2.528
macrocell38 U(0,0) 1 \Digital_PWM:PWMUDB:prevCompare2\ SETUP 3.510
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 118.092 MHz 8.468 47.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 2.430
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 2.528
macrocell40 U(0,0) 1 \Digital_PWM:PWMUDB:status_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\FreqDiv_1:count_5\/q \FreqDiv_1:count_3\/main_1 104.646 MHz 9.556 990.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
Route 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q \FreqDiv_1:count_3\/main_1 4.796
macrocell26 U(2,4) 1 \FreqDiv_1:count_3\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_5\/q Net_1476/main_2 111.074 MHz 9.003 990.997
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
Route 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q Net_1476/main_2 4.243
macrocell12 U(2,4) 1 Net_1476 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_5\/q \FreqDiv_1:count_2\/main_1 116.414 MHz 8.590 991.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
Route 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q \FreqDiv_1:count_2\/main_1 3.830
macrocell27 U(3,4) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_5\/q \FreqDiv_1:count_5\/main_1 116.713 MHz 8.568 991.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/clock_0 \FreqDiv_1:count_5\/q 1.250
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ \FreqDiv_1:count_5\/q \FreqDiv_1:count_5\/main_1 3.808
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_2\/main_0 119.918 MHz 8.339 991.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,4) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_2\/main_0 3.579
macrocell27 U(3,4) 1 \FreqDiv_1:count_2\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_1\/main_0 119.918 MHz 8.339 991.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,4) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_1\/main_0 3.579
macrocell28 U(3,4) 1 \FreqDiv_1:count_1\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_3\/main_0 119.976 MHz 8.335 991.665
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,4) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_3\/main_0 3.575
macrocell26 U(2,4) 1 \FreqDiv_1:count_3\ SETUP 3.510
Clock Skew 0.000
Net_1476/q Net_1476/main_0 121.242 MHz 8.248 991.752
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,4) 1 Net_1476 Net_1476/clock_0 Net_1476/q 1.250
macrocell12 U(2,4) 1 Net_1476 Net_1476/q Net_1476/main_0 3.488
macrocell12 U(2,4) 1 Net_1476 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q Net_1476/main_1 121.966 MHz 8.199 991.801
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,4) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q Net_1476/main_1 3.439
macrocell12 U(2,4) 1 Net_1476 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_0\/main_0 121.966 MHz 8.199 991.801
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,4) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_0\/main_0 3.439
macrocell29 U(2,4) 1 \FreqDiv_1:count_0\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 2.140
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:status_0\/q \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_0 2.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ \PWM_Sample_Buffer:PWMUDB:status_0\/clock_0 \PWM_Sample_Buffer:PWMUDB:status_0\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:status_0\ \PWM_Sample_Buffer:PWMUDB:status_0\/q \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/status_0 2.897
statusicell1 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_1 2.702
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\ \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/clock \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_Sample_Buffer:PWMUDB:control_7\ \PWM_Sample_Buffer:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_1 2.342
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
Net_491__SYNC/out Net_600/clk_en 2.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 Net_491__SYNC Net_491__SYNC/clock Net_491__SYNC/out 0.350
Route 1 Net_491__SYNC_OUT Net_491__SYNC/out Net_600/clk_en 2.615
macrocell18 U(3,1) 1 Net_600 HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb \PWM_Sample_Buffer:PWMUDB:status_0\/main_1 3.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb 0.720
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_eq\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb \PWM_Sample_Buffer:PWMUDB:status_0\/main_1 2.612
macrocell16 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb \PWM_Sample_Buffer:PWMUDB:prevCompare1\/main_0 3.346
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/clock \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb 0.720
Route 1 \PWM_Sample_Buffer:PWMUDB:cmp1_eq\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ce0_comb \PWM_Sample_Buffer:PWMUDB:prevCompare1\/main_0 2.626
macrocell15 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:prevCompare1\/q \PWM_Sample_Buffer:PWMUDB:status_0\/main_0 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ \PWM_Sample_Buffer:PWMUDB:prevCompare1\/clock_0 \PWM_Sample_Buffer:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:prevCompare1\ \PWM_Sample_Buffer:PWMUDB:prevCompare1\/q \PWM_Sample_Buffer:PWMUDB:status_0\/main_0 2.289
macrocell16 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
Net_205/q Trigger_Block/main_2 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,1) 1 Net_205 Net_205/clock_0 Net_205/q 1.250
Route 1 Net_205 Net_205/q Trigger_Block/main_2 2.297
macrocell35 U(2,1) 1 Trigger_Block HOLD 0.000
Clock Skew 0.000
Trigger_Block/q Trigger_Block/main_1 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,1) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
macrocell35 U(2,1) 1 Trigger_Block Trigger_Block/q Trigger_Block/main_1 2.297
macrocell35 U(2,1) 1 Trigger_Block HOLD 0.000
Clock Skew 0.000
\PWM_Sample_Buffer:PWMUDB:trig_last\/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_2 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ \PWM_Sample_Buffer:PWMUDB:trig_last\/clock_0 \PWM_Sample_Buffer:PWMUDB:trig_last\/q 1.250
Route 1 \PWM_Sample_Buffer:PWMUDB:trig_last\ \PWM_Sample_Buffer:PWMUDB:trig_last\/q \PWM_Sample_Buffer:PWMUDB:runmode_enable\/main_2 2.300
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
External_Trigger(0)_SYNC/out Net_550/main_3 3.245
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 External_Trigger(0)_SYNC External_Trigger(0)_SYNC/clock External_Trigger(0)_SYNC/out 0.350
Route 1 Net_533_SYNCOUT External_Trigger(0)_SYNC/out Net_550/main_3 2.895
macrocell22 U(3,2) 1 Net_550 HOLD 0.000
Clock Skew 0.000
Net_600/q Net_601/main_1 4.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_601/main_1 3.206
macrocell19 U(3,0) 1 Net_601 HOLD 0.000
Clock Skew 0.000
Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 4.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q \EdgeDetect_CaptureComplete:last\/main_0 3.226
macrocell21 U(3,2) 1 \EdgeDetect_CaptureComplete:last\ HOLD 0.000
Clock Skew 0.000
Net_600/q Net_550/main_2 4.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_550/main_2 3.226
macrocell22 U(3,2) 1 Net_550 HOLD 0.000
Clock Skew 0.000
Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 5.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,1) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q \EdgeDetect_Trigger:last\/main_1 4.104
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
Trigger_Block/q \Trigger_Status:sts:sts_reg\/status_1 9.020
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,1) 1 Trigger_Block Trigger_Block/clock_0 Trigger_Block/q 1.250
Route 1 Trigger_Block Trigger_Block/q Net_510/main_2 4.104
macrocell7 U(2,3) 1 Net_510 Net_510/main_2 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
Net_600/q \Trigger_Status:sts:sts_reg\/status_2 9.043
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_600 Net_600/clock_0 Net_600/q 1.250
Route 1 Net_600 Net_600/q Net_509/main_0 4.140
macrocell8 U(3,3) 1 Net_509 Net_509/main_0 Net_509/q 3.350
Route 1 Net_509 Net_509/q \Trigger_Status:sts:sts_reg\/status_2 2.303
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 2.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,3) 1 \Wave_Control:Sync:ctrl_reg\ \Wave_Control:Sync:ctrl_reg\/busclk \Wave_Control:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_564 \Wave_Control:Sync:ctrl_reg\/control_0 \Wave_DAC:Net_134\/main_0 2.324
macrocell30 U(2,3) 1 \Wave_DAC:Net_134\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_6 Net_633/main_0 3.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_6 0.360
Route 1 ARM \Trigger_Control:Sync:ctrl_reg\/control_6 Net_633/main_0 2.935
macrocell32 U(2,1) 1 Net_633 HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 4.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 4.205
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_0 5.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/cs_addr_0 5.067
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 5.938
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 5.578
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 5.982
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 5.622
macrocell16 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.501
statusicell1 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 7.728
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 5.578
datapathcell1 U(2,4) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/cs_addr_0 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb 1.790
Route 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(2,3) 1 \PWM_Sample_Buffer:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 Net_633/main_1 9.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 0.360
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger/main_0 3.240
macrocell3 U(2,1) 1 Trigger Trigger/main_0 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_633/main_1 2.916
macrocell32 U(2,1) 1 Net_633 HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 Net_205/main_0 9.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 0.360
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger/main_0 3.240
macrocell3 U(2,1) 1 Trigger Trigger/main_0 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_205/main_0 2.916
macrocell33 U(2,1) 1 Net_205 HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 Net_641/main_0 9.867
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 0.360
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger/main_0 3.240
macrocell3 U(2,1) 1 Trigger Trigger/main_0 Trigger/q 3.350
Route 1 Trigger Trigger/q Net_641/main_0 2.917
macrocell31 U(2,1) 1 Net_641 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_4 Net_550/main_0 2.686
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_4 0.360
Route 1 Net_265 \Trigger_Control:Sync:ctrl_reg\/control_4 Net_550/main_0 2.326
macrocell22 U(3,2) 1 Net_550 HOLD 0.000
Clock Skew 0.000
Net_601/q Net_601/main_2 3.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,0) 1 Net_601 Net_601/clock_0 Net_601/q 1.250
macrocell19 U(3,0) 1 Net_601 Net_601/q Net_601/main_2 2.680
macrocell19 U(3,0) 1 Net_601 HOLD 0.000
Clock Skew 0.000
Net_550/q Net_550/main_1 4.027
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,2) 1 Net_550 Net_550/clock_0 Net_550/q 1.250
macrocell22 U(3,2) 1 Net_550 Net_550/q Net_550/main_1 2.777
macrocell22 U(3,2) 1 Net_550 HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_6 Net_601/main_0 4.185
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_6 0.360
Route 1 ARM \Trigger_Control:Sync:ctrl_reg\/control_6 Net_601/main_0 3.825
macrocell19 U(3,0) 1 Net_601 HOLD 0.000
Clock Skew 0.000
\EdgeDetect_Trigger:last\/q \Trigger_Status:sts:sts_reg\/status_1 7.201
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ \EdgeDetect_Trigger:last\/clock_0 \EdgeDetect_Trigger:last\/q 1.250
Route 1 \EdgeDetect_Trigger:last\ \EdgeDetect_Trigger:last\/q Net_510/main_1 2.285
macrocell7 U(2,3) 1 Net_510 Net_510/main_1 Net_510/q 3.350
Route 1 Net_510 Net_510/q \Trigger_Status:sts:sts_reg\/status_1 2.316
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
\EdgeDetect_CaptureComplete:last\/q \Trigger_Status:sts:sts_reg\/status_2 7.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,2) 1 \EdgeDetect_CaptureComplete:last\ \EdgeDetect_CaptureComplete:last\/clock_0 \EdgeDetect_CaptureComplete:last\/q 1.250
Route 1 \EdgeDetect_CaptureComplete:last\ \EdgeDetect_CaptureComplete:last\/q Net_509/main_1 2.907
macrocell8 U(3,3) 1 Net_509 Net_509/main_1 Net_509/q 3.350
Route 1 Net_509 Net_509/q \Trigger_Status:sts:sts_reg\/status_2 2.303
statuscell1 U(3,3) 1 \Trigger_Status:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_0 \EdgeDetect_Trigger:last\/main_0 11.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_0 0.360
Route 1 Net_235 \Trigger_Control:Sync:ctrl_reg\/control_0 Trigger/main_0 3.240
macrocell3 U(2,1) 1 Trigger Trigger/main_0 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_1 \EdgeDetect_Trigger:last\/main_0 11.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_1 0.360
Route 1 Net_236 \Trigger_Control:Sync:ctrl_reg\/control_1 Trigger/main_1 3.408
macrocell3 U(2,1) 1 Trigger Trigger/main_1 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_3 \EdgeDetect_Trigger:last\/main_0 11.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_3 0.360
Route 1 TrigMux_1 \Trigger_Control:Sync:ctrl_reg\/control_3 Trigger/main_3 3.417
macrocell3 U(2,1) 1 Trigger Trigger/main_3 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_2 \EdgeDetect_Trigger:last\/main_0 14.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_2 0.360
Route 1 TrigMux_0 \Trigger_Control:Sync:ctrl_reg\/control_2 Trigger/main_2 6.233
macrocell3 U(2,1) 1 Trigger Trigger/main_2 Trigger/q 3.350
Route 1 Trigger Trigger/q \EdgeDetect_Trigger:last\/main_0 4.561
macrocell20 U(2,3) 1 \EdgeDetect_Trigger:last\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.580
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 0.580
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 1.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/clock \PRS:sC16:PRSdp:u0\/sol_msb 1.070
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/cfbi 1.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 0.580
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/cfbo 1.270
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u1\/sir 2.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ \PRS:sC16:PRSdp:u1\/clock \PRS:sC16:PRSdp:u1\/cmsbo 0.580
Route 1 \PRS:sC16:PRSdp:u1.cmsbo__sig\ \PRS:sC16:PRSdp:u1\/cmsbo \PRS:sC16:PRSdp:u0\/cmsbi 0.000
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cmsbi \PRS:sC16:PRSdp:u0\/sol_msb 2.250
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.559
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 3.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/clk_en 3.586
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 3.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/clk_en 3.602
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 3.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cs_addr_0 3.610
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/cfbi 4.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.559
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/cfbo 1.080
Route 1 \PRS:sC16:PRSdp:u0.cfbo__sig\ \PRS:sC16:PRSdp:u0\/cfbo \PRS:sC16:PRSdp:u1\/cfbi 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
\PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u1\/sir 5.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \PRS:ClkSp:CtrlReg\ \PRS:ClkSp:CtrlReg\/clock \PRS:ClkSp:CtrlReg\/control_0 0.360
Route 1 \PRS:enable_final\ \PRS:ClkSp:CtrlReg\/control_0 \PRS:sC16:PRSdp:u0\/cs_addr_0 3.559
datapathcell3 U(2,0) 1 \PRS:sC16:PRSdp:u0\ \PRS:sC16:PRSdp:u0\/cs_addr_0 \PRS:sC16:PRSdp:u0\/sol_msb 1.750
Route 1 \PRS:sC16:PRSdp:u0.sol_msb__sig\ \PRS:sC16:PRSdp:u0\/sol_msb \PRS:sC16:PRSdp:u1\/sir 0.000
datapathcell4 U(3,0) 1 \PRS:sC16:PRSdp:u1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Digital_PWM:PWMUDB:status_1\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_1 1.507
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,0) 1 \Digital_PWM:PWMUDB:status_1\ \Digital_PWM:PWMUDB:status_1\/clock_0 \Digital_PWM:PWMUDB:status_1\/q 1.250
Route 1 \Digital_PWM:PWMUDB:status_1\ \Digital_PWM:PWMUDB:status_1\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_1 2.257
statusicell2 U(0,0) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:status_0\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_0 1.509
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(0,0) 1 \Digital_PWM:PWMUDB:status_0\ \Digital_PWM:PWMUDB:status_0\/clock_0 \Digital_PWM:PWMUDB:status_0\/q 1.250
Route 1 \Digital_PWM:PWMUDB:status_0\ \Digital_PWM:PWMUDB:status_0\/q \Digital_PWM:PWMUDB:genblk8:stsreg\/status_0 2.259
statusicell2 U(0,0) 1 \Digital_PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:genblk1:ctrlreg\/control_7 \Digital_PWM:PWMUDB:runmode_enable\/main_0 2.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,0) 1 \Digital_PWM:PWMUDB:genblk1:ctrlreg\ \Digital_PWM:PWMUDB:genblk1:ctrlreg\/clock \Digital_PWM:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \Digital_PWM:PWMUDB:control_7\ \Digital_PWM:PWMUDB:genblk1:ctrlreg\/control_7 \Digital_PWM:PWMUDB:runmode_enable\/main_0 2.272
macrocell36 U(0,0) 1 \Digital_PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 3.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 0.810
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:prevCompare2\/main_0 2.528
macrocell38 U(0,0) 1 \Digital_PWM:PWMUDB:prevCompare2\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 3.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 0.810
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb \Digital_PWM:PWMUDB:status_1\/main_1 2.528
macrocell40 U(0,0) 1 \Digital_PWM:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 3.346
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb 0.810
Route 1 \Digital_PWM:PWMUDB:cmp2_eq\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/ce1_comb Net_916/main_1 2.536
macrocell42 U(0,0) 1 Net_916 HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:prevCompare2\/q \Digital_PWM:PWMUDB:status_1\/main_0 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(0,0) 1 \Digital_PWM:PWMUDB:prevCompare2\ \Digital_PWM:PWMUDB:prevCompare2\/clock_0 \Digital_PWM:PWMUDB:prevCompare2\/q 1.250
Route 1 \Digital_PWM:PWMUDB:prevCompare2\ \Digital_PWM:PWMUDB:prevCompare2\/q \Digital_PWM:PWMUDB:status_1\/main_0 2.232
macrocell40 U(0,0) 1 \Digital_PWM:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:prevCompare1\/q \Digital_PWM:PWMUDB:status_0\/main_0 3.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(0,0) 1 \Digital_PWM:PWMUDB:prevCompare1\ \Digital_PWM:PWMUDB:prevCompare1\/clock_0 \Digital_PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \Digital_PWM:PWMUDB:prevCompare1\ \Digital_PWM:PWMUDB:prevCompare1\/q \Digital_PWM:PWMUDB:status_0\/main_0 2.234
macrocell39 U(0,0) 1 \Digital_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 3.606
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:status_0\/main_1 2.826
macrocell39 U(0,0) 1 \Digital_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 3.619
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(0,0) 1 \Digital_PWM:PWMUDB:sP8:pwmdp:u0\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/clock \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \Digital_PWM:PWMUDB:cmp1_less\ \Digital_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \Digital_PWM:PWMUDB:prevCompare1\/main_0 2.839
macrocell37 U(0,0) 1 \Digital_PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\FreqDiv_1:count_4\/q \FreqDiv_1:count_5\/main_2 4.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/clock_0 \FreqDiv_1:count_4\/q 1.250
Route 1 \FreqDiv_1:count_4\ \FreqDiv_1:count_4\/q \FreqDiv_1:count_5\/main_2 3.092
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q Net_1476/main_7 4.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(2,4) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q Net_1476/main_7 3.117
macrocell12 U(2,4) 1 Net_1476 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_5\/main_3 4.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(2,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_5\/main_3 3.122
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_3\/q \FreqDiv_1:count_4\/main_1 4.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(2,4) 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/clock_0 \FreqDiv_1:count_3\/q 1.250
Route 1 \FreqDiv_1:count_3\ \FreqDiv_1:count_3\/q \FreqDiv_1:count_4\/main_1 3.122
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_1\/q \FreqDiv_1:count_5\/main_5 4.463
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,4) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q \FreqDiv_1:count_5\/main_5 3.213
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_1\/q \FreqDiv_1:count_4\/main_3 4.463
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,4) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q \FreqDiv_1:count_4\/main_3 3.213
macrocell25 U(3,4) 1 \FreqDiv_1:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_1\/q Net_1476/main_6 4.466
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,4) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q Net_1476/main_6 3.216
macrocell12 U(2,4) 1 Net_1476 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q \FreqDiv_1:count_3\/main_4 4.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,4) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
Route 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q \FreqDiv_1:count_3\/main_4 3.227
macrocell26 U(2,4) 1 \FreqDiv_1:count_3\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q Net_1476/main_5 4.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,4) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
Route 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q Net_1476/main_5 3.229
macrocell12 U(2,4) 1 Net_1476 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q \FreqDiv_1:count_5\/main_4 4.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,4) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
Route 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q \FreqDiv_1:count_5\/main_4 3.231
macrocell24 U(3,4) 1 \FreqDiv_1:count_5\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Digital_Out_Control:Sync:ctrl_reg\/control_3 DigOut_4(0)_PAD 25.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,0) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_230 \Digital_Out_Control:Sync:ctrl_reg\/control_3 DigOut_4(0)/pin_input 8.176
iocell18 P0[0] 1 DigOut_4(0) DigOut_4(0)/pin_input DigOut_4(0)/pad_out 15.251
Route 1 DigOut_4(0)_PAD DigOut_4(0)/pad_out DigOut_4(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_4 DigOut_5(0)_PAD 25.269
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,0) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_232 \Digital_Out_Control:Sync:ctrl_reg\/control_4 DigOut_5(0)/pin_input 7.417
iocell21 P0[1] 1 DigOut_5(0) DigOut_5(0)/pin_input DigOut_5(0)/pad_out 15.802
Route 1 DigOut_5(0)_PAD DigOut_5(0)/pad_out DigOut_5(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_2 DigOut_3(0)_PAD 25.259
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,0) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_229 \Digital_Out_Control:Sync:ctrl_reg\/control_2 DigOut_3(0)/pin_input 7.284
iocell17 P15[5] 1 DigOut_3(0) DigOut_3(0)/pin_input DigOut_3(0)/pad_out 15.925
Route 1 DigOut_3(0)_PAD DigOut_3(0)/pad_out DigOut_3(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_5 DigOut_6(0)_PAD 25.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,0) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_233 \Digital_Out_Control:Sync:ctrl_reg\/control_5 DigOut_6(0)/pin_input 8.178
iocell9 P0[5] 1 DigOut_6(0) DigOut_6(0)/pin_input DigOut_6(0)/pad_out 15.023
Route 1 DigOut_6(0)_PAD DigOut_6(0)/pad_out DigOut_6(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_1 DigOut_2(0)_PAD 22.906
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,0) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_228 \Digital_Out_Control:Sync:ctrl_reg\/control_1 DigOut_2(0)/pin_input 6.427
iocell11 P15[1] 1 DigOut_2(0) DigOut_2(0)/pin_input DigOut_2(0)/pad_out 14.429
Route 1 DigOut_2(0)_PAD DigOut_2(0)/pad_out DigOut_2(0)_PAD 0.000
Clock Clock path delay 0.000
\Digital_Out_Control:Sync:ctrl_reg\/control_0 DigOut_1(0)_PAD 22.038
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(3,0) 1 \Digital_Out_Control:Sync:ctrl_reg\ \Digital_Out_Control:Sync:ctrl_reg\/busclk \Digital_Out_Control:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_231 \Digital_Out_Control:Sync:ctrl_reg\/control_0 DigOut_1(0)/pin_input 5.733
iocell10 P15[0] 1 DigOut_1(0) DigOut_1(0)/pin_input DigOut_1(0)/pad_out 14.255
Route 1 DigOut_1(0)_PAD DigOut_1(0)/pad_out DigOut_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ PWM_Clock
Source Destination Delay (ns)
Net_885/q PWMOut_0(0)_PAD 23.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,0) 1 Net_885 Net_885/clock_0 Net_885/q 1.250
Route 1 Net_885 Net_885/q PWMOut_0(0)/pin_input 6.508
iocell15 P1[2] 1 PWMOut_0(0) PWMOut_0(0)/pin_input PWMOut_0(0)/pad_out 15.470
Route 1 PWMOut_0(0)_PAD PWMOut_0(0)/pad_out PWMOut_0(0)_PAD 0.000
Clock Clock path delay 0.000
Net_916/q PWMOutB_0(0)_PAD 22.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(0,0) 1 Net_916 Net_916/clock_0 Net_916/q 1.250
Route 1 Net_916 Net_916/q PWMOutB_0(0)/pin_input 5.738
iocell16 P1[4] 1 PWMOutB_0(0) PWMOutB_0(0)/pin_input PWMOutB_0(0)/pad_out 15.678
Route 1 PWMOutB_0(0)_PAD PWMOutB_0(0)/pad_out PWMOutB_0(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 27.7778ns(36 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 129.685 MHz 7.711 20.067
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 1.210
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.501
statusicell1 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 146.370 MHz 6.832 20.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 1.210
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 5.622
macrocell16 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ RECOVERY -0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 184.672 MHz 5.415 22.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 1.210
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 4.205
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 4.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:runmode_enable\/ar_0 4.205
macrocell14 U(2,2) 1 \PWM_Sample_Buffer:PWMUDB:runmode_enable\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 5.982
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:status_0\/ar_0 5.622
macrocell16 U(3,3) 1 \PWM_Sample_Buffer:PWMUDB:status_0\ REMOVAL 0.000
Clock Skew 0.000
\Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Trigger_Control:Sync:ctrl_reg\ \Trigger_Control:Sync:ctrl_reg\/clock \Trigger_Control:Sync:ctrl_reg\/control_7 0.360
Route 1 Net_398 \Trigger_Control:Sync:ctrl_reg\/control_7 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\/reset 6.501
statusicell1 U(3,2) 1 \PWM_Sample_Buffer:PWMUDB:genblk8:stsreg\ REMOVAL 0.000
Clock Skew 0.000